1. Field of the Invention
This invention relates generally to the cell structure and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and improved process for fabricating a trench MOSFET with improved metal schemes for copper bonding.
2. The Prior Arts
Please refer to FIG. 1 for a Cu bonding compatible bond pad structure of prior art (U.S. Patent application publication No. 20080006951). The disclosed structure includes a buffering structure comprising exposed electrode metal regions 118 of electrode metal layer 114 formed over a TiNi barrier metal layer 112 and non-conductive passivation regions 120 having same material as passivation layer 116. As illustrated, while bonding Cu bonding wire 122, some of the passivation regions 120 were pushed into the electrode metal layer 114 to provide a buffer function to keep Cu bonding wire 122 away from barrier metal layer 112 and the semiconductor device whereunder.
By employing non-conductive passivation material as buffer layer, the structure of prior art shown in FIG. 1 minimized bonding damage on semiconductor device, however, comparing to its advantage, the disadvantages brought by this passivation structure are more significant to a certain extent. First of all, more cost are needed due to the requirement of additional passivation layer deposition, masking and etching; Second, wire bonding resistance is increased because that some Cu bonding area is occupied by the non-conductive passivation layer; Third, bad wire bonding adhesion issue is introduced due to Cu wire contacting with passivation layer in some area. Therefore, it is necessary to provide an improved metal bonding structure with lower cost, lower power consumptions, as well as steady performance.
Please refer to FIGS. 2 to 4 for MOSFETs structures of another prior art (U.S. Pat. No. 6,888,196). In FIG. 2, the trench MOSFET is formed on a heavily doped substrate 200 of a first semiconductor doping type, e.g., N+ dopant, on which an epitaxial layer 202 doped with the same first semiconductor doping type is grown. Inside epitaxial layer 202, a plurality of trench gates 210 are formed over a gate oxide layer 208. Between each trench, there is a body region 212 of a second semiconductor doping type, e.g., P dopant, introduced by Ion Implantation, and N+ source regions 214 near the top surface of P-body area. Said source regions and body regions are connected to source metal 220 via metal plug 216 in source-body contact trench through a layer of oxide interlayer 218. Around the bottom of each metal plug 216, an area of heavily P+ doped 206 is formed to reduce the resistance between source and body region. Metal layer 220 serving as source metal is deposited on the front surface of whole device while metal layer 222 serving as drain metal deposited on the rear side of substrate 200.
As mentioned above, the metal plug 216, e.g., W plug, filled in source-body contact trench connects directly with the front source metal through the contact trench open area in oxide interlayer film 218, in other words, no buffer layer is available while bonding Cu wire upon source metal layer. Therefore, thick front source metal is required to minimize the bonding damage to semiconductor device, leading to extra cost and metal etching complication.
On the other hand, the P+ area 206 underneath trench source-body contact bottom is formed by BF2 Ion Implantation before source-body contact trench's filled with contact material. As the sidewalls of source-body contact trench is perpendicular to the front surface of epitaxial layer, said P+ area can be implanted only around the bottom of source-body contact trench no matter with or without oxide film BF2 Ion Implantation, resulting in a high resistance Rp underneath N+ source and between channel and P+ area. As is known to all, a parasitic N+/PIN will be turned on if Iav*Rp>0.7V where Iav is avalanche current originated from the trench bottom. Therefore, the conventional vertical source contact shown in FIG. 2 also has a poor avalanche capability which significantly affects the performance of whole device.
Another MOSFETs structure with P+ region formed by BF2 Ion Implantation through an oxide film deposited on the contact trench was disclosed in that application, as shown in FIG. 3. The structure here is almost the same as structure in FIG. 2 except for the slope source-body contact trench. However, even if the slope contact trench is helpful to enlarge the P+ area under trench source-body contact during BF2 Ion Implantation, it is still not enough to resolve the high Rp problem as the P+ area is also formed only around the bottom of source-body contact trench. Meanwhile, a similar structure with P+ region formed on both bottom and sidewall of source-body contact trench by BF2 Ion Implantation without through the oxide film of prior art is given in FIG. 4. As there is no oxide film, the P+ area is apparently enlarged to be formed on the sidewall of source-body contact trench besides the bottom, resolving the high Rp issue discussed above. However, anther problem is thus introduced, which is that the N+ concentration on contact trench sidewalls will be reduced as a result of compensation by BF2 Ion Implantation due to no oxide film as stopper, causing high source contact resistance.
At the same time, structures illustrated in FIG. 3 and FIG. 4 both required thick front metal to minimize the bonding damage to semiconductor device due to the lack of buffer layer.
Accordingly, it would be desirable to provide a trench MOSFET cell with improved metal schemes and improved source contact structure to avoid those problems mentioned above.